The disclosed embodiments relate to NAND Flash memory and, more specifically, to systems and methods for enabling variable-length NAND Flash pages.
A fundamental and readable unit of NAND Flash solid-state drive (SSD) devices is the “sector” or “page.” SSDs store all data on a number of pages arranged within multiple logical layers of the SSD. Early, and current, traditional solid-state drive (SSD) devices utilized fixed sector sizes of 512 bytes or 4096 bytes (4 KB). More recently, SSDs have supported “variable sector sizes.” A variable sector size refers to supporting sector sizes beyond standard 512B and 4 KB sector sizes including random sector sizes. Advances in computer architecture, such as the proliferation of NVM Express (NVMe) devices, have resulted in many options of sector sizes including 520, 528, 4104, 4160, and 4224-byte page sizes. Variable sector sizes are designed to allow users and applications to insert additional management information together with actual data stored on SSDs in each sector.
The need to store additional data in sectors arises due to the fundamental characteristics of NAND Flash memory. Specifically, management data for a given page is ideally stored in a region of the page so that the management data can be read along with the page, eliminating multiple reads. Additionally, the logical block address (LBA) of each sector is stored as management data in the sector, usually in an out-of-band (OOB) region of the sector. LBA data is stored within a sector so that the LBA to physical block address (PBA) mapping can be re-built by reading content of individual sectors.
The use of variable page sizes results in the use of varying error correction code (ECC) and cyclical redundancy check (CRC) mechanisms. The requirement that multiple ECC and CRC mechanisms be used increase the overhead required by a NAND Flash controller.
Additionally, NAND Flash fabrication increasingly “stacks” multiple chips within a single package in order to increase the density of the package while retaining a smaller form factor. While these three-dimensional stacking techniques improve the capacity of the NAND Flash package, the proximity of chips drastically increases the noise present on the channel as well as varies access time to data within the NAND Flash package. The increase in noise results in higher levels of ECC and CRC redundancy needed to both detect and, if possible, correct errors within the package data.
Further, the increase in program and erase (“P/E”) cycles results in a higher error rate due to the nature of NAND Flash circuitry. Specifically, each P/E cycle reduces the integrity of the underlying transistors in the NAND Flash package, resulting in a higher level of noise (and, thus, a higher redundancy of ECC and CRC bits).
In general, current systems handle this increased noise by providing stronger error correction schemes on the fly. This technique, however, requires that the error correction circuitry switch to a lower code rate in order to provide strong fault tolerance. This decreasing of code rate results in lower throughput of the NAND Flash package. Thus, current systems result in degraded NAND Flash performance over time due to the combination of variable page sizes, three-dimensional stacking, and higher P/E cycles.